
Senior ASIC Verification Engineer
- Heredia
- Permanente
- Tiempo completo
- Lead RTL design, simulation, verification, timing closure, and physical implementation efforts.
- Drive architecture decisions and contribute to system-level design trade-offs.
- Mentor and guide junior engineers in design methodologies and best practices.
- Collaborate cross-functionally to define and refine design specifications and verification strategies.
- Own and lead tape-out activities, ensuring quality and schedule adherence.
- Influence and improve design processes and methodologies.
- Bachelor's degree on Electrical Engineer, Electronics, or related field.
- 5+ year of experience in Digital Integrated Circuit design.
- Proven track record of successful tape-outs and post-silicon validation.
- Demonstrated experience architecting and leading UVM-based verification environments from the ground up, including testbench development, methodology definition, and team enablement.
- Advanced proficiency with Linux and Cadence tools (or equivalent).
- Advanced English Level
- Deep expertise in ASIC digital design flow, including architecture definition and backend implementation.
- Strong background in DFT methodologies (ATPG, LBIST, MBIST).
- Demonstrated success in low-power design for high-reliability applications.
- Experience in regulated industries (e.g., medical, aerospace) with knowledge of quality systems and compliance.